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e see new design recommendations december 1997 order number: 290531-005 n intel smartvoltage technology ? 5 v or 12 v program/erase ? 3.3 v or 5 v read operation n very high-performance read ? 5 v: 60 ns access time ? 3 v: 110 ns access time n low power consumption ? max 60 ma read current at 5 v ? max 30 ma read current at 3.3 v C3.6 v n x8/x16-selectable input/output bus ? 28f200 for high performance 16- or 32-bit cpus n x8-only input/output architecture ? 28f002b for space-constrained 8-bit applications n optimized array blocking architecture ? one 16-kb protected boot block ? two 8-kb parameter blocks ? 96-kb and 128-kb main blocks ? top or bottom boot locations n extended temperature operation ? C40 c to +85 c n extended block erase cycling ? 100,000 cycles at commercial temp ? 10,000 cycles at extended temp n automated word/byte program and block erase ? command user interface ? status registers ? erase suspend capability n sram-compatible write interface n automatic power savings feature n reset/deep power-down input ? 0.2 a i cc typical ? provides reset for boot operations n hardware data protection feature ? absolute hardware-protection for boot block ? write lockout during power transitions n industry-standard surface mount packaging ? 40-, 48-, 56-lead tsop ? 44-lead psop n footprint upgradeable to 4-mbit and 8-mbit boot block flash memories n etox? iv flash technology new design recommendations: for new 2.7 v C3.6 v v cc designs with this device, intel recommends using the smart 3 advanced boot block. reference smart 3 advanced boot block 4-mbit, 8-mbit, 16-mbit flash memory family datasheet, order number 290580. for new 5 v v cc designs with this device, intel recommends using the 2-mbit smart 5 boot block. reference smart 5 flash memory family 2, 4, 8 mbit datasheet, order number 290599. these documents are also available at intels website, http://www.intel.com/design/flcomp. reference only 2-mbit smartvoltage boot block flash memory family 28f200bv-t/b, 28f200cv-t/b, 28f002bv-t/b
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f200bv-t/b, 28f200cv-t/b, 28f002bv-t/b may contain design defects or errors known as errata. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 8021-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation, 1997 cg-041493 *third-party brands and names are the property of their respective owners..
e 2-mbit smartvoltage boot block family 3 see new design recommendations contents page page 1.0 product family overview.....................5 1.1 new features in the smartvoltage products 5 1.2 main features ..............................................5 1.3 applications..................................................6 1.4 pinouts.........................................................7 1.5 pin descriptions .........................................11 2.0 product description............................13 2.1 memory blocking organization...................13 2.1.1 one 16-kb boot block.........................13 2.1.2 two 8-kb parameter blocks................13 2.1.3 one 96-kb + one 128-kb main block.13 3.0 product family principles of operation ................................................15 3.1 bus operations ..........................................15 3.2 read operations ........................................15 3.2.1 read array ..........................................15 3.2.2 intelligent identifiers ............................17 3.3 write operations ........................................17 3.3.1 command user interface (cui) ...........17 3.3.2 status register....................................20 3.3.3 program mode.....................................21 3.3.4 erase mode .........................................21 3.4 boot block locking ....................................22 3.4.1 v pp = v il for complete protection .......22 3.4.2 wp# = v il for boot block locking .......22 3.4.3 rp# = v hh or wp# = v ih for boot block unlocking ...........................................22 3.4.4 upgrade note for 8-mbit 44-psop package .............................................22 3.5 power consumption...................................26 3.5.1 active power .......................................26 3.5.2 automatic power savings (aps) .........26 3.5.3 standby power ....................................26 3.5.4 deep power-down mode.....................26 3.6 power-up/down operation.........................26 3.6.1 rp# connected to system reset .......26 3.6.2 v cc , v pp and rp# transitions............27 3.7 power supply decoupling ..........................27 3.7.1 v pp trace on printed circuit boards ..27 4.0 electrical specifications..................28 4.1 absolute maximum ratings........................28 4.2 commercial operating conditions ..............28 4.2.1 applying v cc voltages.........................29 4.3 capacitance ...............................................29 4.4 dc characteristics commercial ...............30 4.5 ac characteristicscommercial ...............34 4.6 ac characteristicswe#-controlled write operationscommercial ..........................37 4.7 ac characteristicsce#-controlled write operationscommercial ..........................40 4.8 erase and program timingscommercial.43 4.9 extended operating conditions..................43 4.9.1 applying v cc voltages.........................44 4.10 capacitance .............................................44 4.11 dc characteristicsextended temperature operations............................45 4.12 ac characteristicsread only operationsextended temperature .........49 4.13 ac characteristicswe#-controlled write operations extended temperature ........50 4.14 ac characteristicsce#-controlled write operations extended temperature ........52 4.15 erase and program timingsextended temperature..............................................53 5.0 ordering information..........................54 6.0 additional information .......................55 related intel information ..................................55
2-mbit smartvoltage boot block family e 4 see new design recommendations revision history number description -001 initial release of datasheet. -002 status changed from product preview to preliminary 28f200cv/ce/be references and information added throughout. 2.7 v ce/be specs added throughout. the following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1, 3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2. note 2 added to figure 3 to clarify 28f008b pinout vs. 28f008sa. sentence about program and erase wsm timeout deleted from section 3.3.3, 3.3.4. erroneous arrows leading out of error states deleted from flowcharts in figs. 9, 10. sections 5.1, 6.1 changed to applying v cc voltages. these sections completely changed to clarify v cc ramp requirements. i ppd 3.3 v commercial spec changed from 10 to 5 m a. capacitance tables added after commercial and extended dc characteristics tables. test and slew rate notes added to figs. 12, 13, 19, 20, 21. test configuration drawings (fig. 14, 22) consolidated into one, with component values in table. (component values also rounded off). t elfl , t elfh , t avfl changed from 7 to 5 ns for 3.3 v bv-60 commercial and 3.3 v tbv-80 extended, 10 to 5 ns for 3.3 v bv-80 and bv-120 commercial. t whax and t ehax changed from 10 to 0 ns. t phwl changed from 1000 ns to 800 ns for 3.3 v bv-80, bv-120 commercial. t phel changed from 1000 ns to 800 ns for 3.3 v bv-60, bv-80, and bv-120 commercial. -003 applying v cc voltages (sections 5.1 and 6.1) rewritten for clarity. minor cosmetic changes/edits. -004 corrections: this pin not available on 44-psop inaccurate statement removed from pin description for wp# pin; spec t qwl corrected to t qvvl; intelligent identifier values corrected; intel386? ex block diagram updated because new 386 specs require less glue logic. max program times for parameter and 96-kb main block added. specs t elfl and t elfh changed from 5 ns (max) to 0 ns (min). specs t ehqz and t hqz improved. new specs t plph and t plqz added from specification update document (297612). -005 corrections: figure 4, corrected pin designation 3 to nc from a 17 on pa28f200. corrected typographical errors in ordering information . added new design recommendations section to cover page. updated erase suspend/resume flowchart
e 2-mbit smartvoltage boot block family 5 see new design recommendations 1.0 product family overview this datasheet contains the specifications for the two branches of products in the smartvoltage 2-mbit boot block flash memory family. these -bv/cv suffix products offer 3.0 v C3.6 v operation and also operate at 5 v for high-speed access times. throughout this datasheet, the 28f200 refers to all x8/x16 2-mbit products, while 28f002b refers to all x8 2-mbit boot block products. section 1.0 provides an overview of the flash memory family including applications, pinouts and pin descriptions. sections 2.0 and 3.0 describe the memory organization and operation for these products. section 4.0 contains the familys operating specifications. finally, sections 5.0 and 6.0 provide ordering and document reference information. 1.1 new features in the smartvoltage products the smartvoltage boot block flash memory family offers identical operation with the bx/bl 12 v program products, except for the differences listed below. all other functions are equivalent to current products, including signatures, write commands, and pinouts. wp# pin has replaced a du (dont use) pin. connect the wp# pin to control signal or to v cc or gnd (in this case, a logic-level signal can be placed on du pin). refer to tables 2 and 9 to see how the wp# pin works. 5 v program/erase operation has been added. if switching v pp for write protection, switch to gnd (not 5 v) for complete write protection. to take advantage of 5 v write-capability, allow for connecting 5 v to v pp and disconnecting 12 v from v pp line. enhanced circuits optimize low v cc performance, allowing operation down to v cc = 3.0 v. if you are using bx/bl 12 v v pp boot block products today, you should account for the differences listed above and also allow for connecting 5 v to v pp and disconnecting 12 v from v pp line, if 5 v writes are desired. 1.2 main features intels smartvoltage technology is the most flexible voltage solution in the flash industry, providing two discrete voltage supply pins: v cc for read operation, and v pp for program and erase operation. discrete supply pins allow system designers to use the optimal voltage levels for their design. this product family, specifically the 28f200bv/cv, and 28f002bv provide program/ erase capability at 5 v or 12 v. the 28f200bv/cv and 28f002bv allow reads with v cc at 3.3 v 0.3 v or 5 v. since many designs read from the flash memory a large percentage of the time, read operation using the 3.3 v ranges can provide great power savings. if read performance is an issue, however, 5 v v cc provides faster read access times. for program and erase operations, 5 v v pp operation eliminates the need for in system voltage converters, while 12 v v pp operation provides faster program and erase for situations where 12 v is available, such as manufacturing or designs where 12 v is in-system. for design simplicity, however, just hook up v cc and v pp to the same 5 v 10% source. the 28f200/28f002b boot block flash memory family is a high-performance, 2-mbit (2,097,152 bit) flash memory family organized as either 256 kwords of 16 bits each (28f200 only) or 512 kbytes of 8 bits each (28f200 and 28f002b). table 1. smartvoltage provides total voltage flexibility product bus v cc v pp name width 3.3 v 0.3 v 5 v 5% 5 v 10% 5 v 10% 12 v 5% 28f002bv-t/b x8 ???? 28f200bv-t/b x8 or x16 ???? 28f200cv-t/b x8 or x16 ????
2-mbit smartvoltage boot block family e 6 see new design recommendations separately erasable blo cks, including a hardware- lockable boot block (16,384 bytes), two parameter blocks (8, 192 bytes each) and main blo cks (one block of 98,304 bytes and one block of 131,072 bytes), define the boot block flash family architecture. see figures 7 and 8 for memory maps. each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. the boot block is located at either the top (denoted by -t suffix) or the bottom ( -b suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. the hardware-lockable boot block provides complete code security for the kernel code required for system initialization. locking and unlocking of the boot block is controlled by wp# and/or rp# (see section 3.4 for details). the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. the status register (sr) indicates the status of the wsm and whether it successfully completed the desired program or erase operation. program and erase automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the cui. data programming is performed in word (28f200 family) or byte (28f200 or 28f002b families) increments. each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. the 2-mbit smartvoltage boot block flash memory family is also designed with an automatic power savings (aps) feature which minimizes system battery current drain, allowing for very low power designs. to provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by turning most of the flash memorys circuitry off. this mode is controlled by the rp# pin and its usage is discussed in section 3.5, along with other power consumption issues. additionally, the rp# pin provides protection against unwanted command writes due to invalid system bus c onditions that may occur during system reset and power-up/down sequences. for example, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system com ponents, the flash memory could remain in a non-read mode, such as erase. consequently, the system reset signal should be tied to rp# to reset the memory to normal read mode upon activation of the reset signal. see section 3.6. the 28f200 provides both byte-wide or word-wide input/output, which is controlled by the byte# pin. please see table 2 and figure 16 for a detailed description of byte# operations, especially the usage of the dq 15 /a C1 pin. the 28f200 products are available in a rom/eprom-compatible pinout and housed in the 44-lead psop (plastic small outline) package, the 48-lead tsop (thin small outline, 1.2 mm thick) package and the 56-lead tsop as shown in figures 4, 5 and 6, respectively. the 28f002 products are available in the 40-lead tsop package as shown in figure 3. refer to the dc characteristics , section 4.4 (commercial temperature) and section 4.11 (extended temperature), for complete current and voltage specifications. refer to the ac characteristics , section 4.5 (commercial temperature) and section 4.12 (extended temperature), for read, write and erase performance specifications. 1.3 applications the 2-mbit boot block flash memory family combines high-density, low-power, high- performance, cost-effective flash memories with blocking and hardware protection capabilities. their flexibility and versatility reduce costs throughout the product life cycle. flash memory is i deal for just-in- time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. when your product is in the end-users hands, and updates or feature enhancements become necessary, flash memory reduces the update costs by allowing user-performed code changes instead of costly product returns or technician calls.
e 2-mbit smartvoltage boot block family 7 see new design recommendations the 2-mbit boot block flash memory family provides full-function, blocked flash memories suitable for a wide range of applications. these applications include extended pc bios and rom-able applications storage, digital cellular phone program and data storage, telecommunication boot/firmware, printer firmware/font storage and various other embedded applications where program and data storage are required. reprogrammable systems, such as pers onal computers, are ideal applications for the 2-mbit flash memory products. increasing software sophistication greatens the probability that a code update will be required after the pc is shipped. for example, the emerging of plug and play standard in desktop and portable pcs enables auto- configuration of isa and pci add-in cards. however, since the plug and play specification continues to evolve, a flash bios provides a cost- effective capability to update existing pcs. in addition, the parameter blo cks are i deal for storing the required auto-configuration parameters, allowing you to integrate the bios prom and parameter storage eeprom into a single component, reducing parts costs while increasing functionality. the 2-mbit flash memory products are also excellent design solutions for digital cellular phone and telecommunication switching applications requiring very low power consumption, high- performance, high-density storage capability, modular software designs, and a small form factor package. the 2-mbits blocking scheme allows for easy segmentation of the embedded code with 16 kbytes of hardware-protected boot code, four main blocks of program c ode and two parameter blocks of 8 kbytes each for fr equently updated data storage and diagnostic messages (e.g., phone numbers, authorization codes). intels boot block architecture provides a flexible voltage solution for the different design needs of various applications. the asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. the boot block provides a secure boot prom; the parameter blocks can emulate eeprom functionality for parameter store with proper software techniques; and the main blo cks provide code and data storage with access times fast enough to execute code in place, decreasing ram requirements. 1.4 pinouts intels smartvoltage boot block architecture provides upgrade paths in every package pinout to the 4 or 8-mbit density. the 28f002b 40-lead tsop pinout for space-constrained designs is shown in figure 3. the 28f200 44-lead psop pinout follows the industry-standard rom/eprom pinout, as shown in figure 4. for designs that require x16 operation but have space concerns, refer to the 48-lead pinout in figure 5. furthermore, the 28f200 56-lead tsop pinout shown in figure 6 provides compatibility with bx/bl family product packages. pinouts for the corresponding 4-mbit and 8-mbit components are also provided for convenient reference. 2-mbit pinouts are given on the chip illustration in the center, with 4-mbit and 8-mbit pinouts going outward from the center.
2-mbit smartvoltage boot block family e 8 see new design recommendations i386? ex cpu (25 mhz) a[17:1] cs# rd# wr# ce# a[16:0] oe# we# d[15:0] d[15:0] rp# reset reset 28f200bv-60 note: a data bus buffer may be needed for processor speeds above 25 mhz. 0530_01 figure 1 . 28f200 interface to intel386? ex microprocessor ucs# 80c188eb -a 15 a 8 ale p1.x wr# rd# resin# system reset we# oe# v pp address latches le address latches le ce# rp# 28f002-t -ad 7 ad 0 a[16:17] dq 0 -dq 7 wp# v cc 10k w p1.x v cc a 0 -a 17 0530_02 figure 2. 28f002b interface to intel80c188eb 8-bit embedded microprocessor
e 2-mbit smartvoltage boot block family 9 see new design recommendations 28f002b boot block 40-lead tsop 10 mm x 20 mm top view 32 31 30 29 28 27 26 25 24 23 22 21 33 34 35 36 37 38 39 40 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 a 1 a 2 a 3 rp# we# v pp a 16 a 15 a 7 a 6 a 5 a 4 a 14 a 13 a 8 a 9 a 11 a 12 wp# dq 7 ce# oe# gnd a 0 dq 6 dq 5 dq 4 dq 2 dq 1 dq 0 v cc dq 3 a 17 gnd nc a 10 nc nc nc 28f004b 28f004b a 1 a 2 a 3 rp# we# v pp a 16 a 15 a 7 a 6 a 5 a 4 a 14 a 13 a 8 a 9 a 11 a 12 wp# a 18 dq 7 ce# oe# gnd a 0 dq 6 dq 5 dq 4 dq 2 dq 1 dq 0 v cc dq 3 a 17 gnd nc a 10 nc nc v cc v cc 28f008b dq 7 ce# oe# gnd a 0 dq 6 dq 5 dq 4 dq 2 dq 1 dq 0 v cc dq 3 a 17 gnd nc a 10 nc v cc 28f008b a 1 a 2 a 3 rp# we# v pp a 16 a 15 a 7 a 6 a 5 a 4 a 14 a 13 a 8 a 9 a 11 a 12 wp# a 18 a 19 0530_03 figure 3. the 40-lead tsop offers the smallest form factor for space-constrained applications pa28f200 boot block 44-lead psop 0.525" x 1.110" top view gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 32 31 30 29 28 27 26 25 24 23 33 34 35 36 37 38 39 40 41 42 43 44 ce# wp# gnd oe# a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 v pp nc ce# wp# gnd oe# a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v pp gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 28f400 28f400 dq 15 -1 /a dq 15 -1 /a ce# gnd oe# a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v pp 28f800 gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 28f800 dq 15 -1 /a a 17 a 17 a 18 0530_04 note: pin 2 is wp# on 2- and 4-mbit devices but a 18 on the 8-mbit because no other pins were available for the high order address. thus, the 8-mbit in the 44-lead psop cannot unlock the boot block without rp# = v hh (12 v). to allow upgrades to the 8 mbit from 2/2 mbit in this package, design pin 2 to control wp# at the 2/4 mbit level and a 18 at the 8-mbit density. see section 3.4 for details. figure 4. the 44-lead psop offers a convenient upgrade from jedec rom standards
2-mbit smartvoltage boot block family e 10 see new design recommendations 28f200 boot block 48-lead tsop 12 mm x 20 mm top view 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 25 26 27 28 29 30 31 32 ce# oe# gnd a 0 v cc gnd byte# a 16 dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 dq 3 ce# oe# gnd a 0 v cc gnd byte# a 16 dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 dq 3 ce# oe# gnd a 0 v cc gnd byte# a 16 dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 dq 3 28f400 28f800 28f400 28f800 1 rp# we# nc nc nc wp# a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp a 17 a 6 a 7 a 4 a 5 a 3 a 2 a rp# we# nc nc nc wp# a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp a 6 a 7 a 4 a 5 a 3 a 2 a rp# we# nc nc nc wp# a 18 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp a 17 a 6 a 7 a 4 a 5 a 3 a 2 a nc nc nc 0530_05 figure 5. the 48-lead tsop offers the smallest form factor for x16 operation 28f200 boot block 56-lead tsop 14 mm x 20 mm top view 28 27 26 25 24 23 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 a 1 a 2 a 3 rp# we# a 15 a 7 a 6 a 5 a 4 a 14 a 13 a 8 a 9 a 11 a 12 nc v pp nc nc nc nc nc nc a 10 wp# nc nc a 1 a 2 a 3 rp# we# a 15 a 7 a 6 a 5 a 4 a 14 a 13 a 8 a 9 a 11 a 12 nc v pp nc nc nc nc nc nc a 10 wp# nc dq 7 ce# oe# gnd a 0 dq 6 dq 5 dq 4 dq 2 dq 1 dq 0 v cc v cc dq 3 gnd nc nc dq 9 dq 10 dq 11 dq 8 byte# dq 15 /a -1 dq 14 dq 13 dq 12 a 16 nc 28f400 28f400 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 32 31 30 29 33 34 35 36 37 38 39 40 dq 7 ce# oe# gnd a 0 dq 6 dq 5 dq 4 dq 2 dq 1 dq 0 v cc v cc dq 3 gnd nc nc dq 9 dq 10 dq 11 dq 8 byte# dq 15 /a -1 dq 14 dq 13 dq 12 a 16 nc a 17 0530_06 figure 6. the 56-lead tsop offers compatibility between 2 and 4 mbits
e 2-mbit smartvoltage boot block family 11 see new design recommendations 1.5 pin descriptions table 2. 28f200/002 pin descriptions symbol type name and function a 0 Ca 17 input address inputs for memory addresses. addresses are internally latched during a write cycle. the 28f200 only has a 0 C a 16 pins, while the 28f002b has a 0 C a 17 . a 9 input address input: when a 9 is at v hh the signature mode is accessed. during this mode, a 0 decodes between the manufacturer and device ids. when byte# is at a logic low, only the lower byte of the signatures are read. dq 15 /a C1 is a dont care in the signature mode when byte# is low. dq 0 Cdq 7 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched during the write cycle. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. dq 8 Cdq 15 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched during the write cycle. outputs array data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (byte# = 0). in the byte-wide mode dq 15 /a C1 becomes the lowest order address for data output on dq 0 Cdq 7 . the 28f002b does not include these dq 8 Cdq 15 pins. ce# input chip enable: activates the devices control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. if ce# and rp# are high, but not at a cmos high level, the standby current will increase due to current flow through the ce# and rp# input stages. oe# input output enable: enables the devices outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command register and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse. rp# input reset/deep power-down: uses three voltage levels (v il , v ih , and v hh ) to control two different functions: reset/deep power-down mode and boot block unlocking. it is backwards-compatible with the bx/bl/bv products. when rp# is at logic low, the device is in reset/deep power-down mode , which puts the outputs at high-z, resets the write state machine, and draws minimum current. when rp# is at logic high, the device is in standard operation . when rp# transitions from logic-low to logic-high, the device defaults to the read array mode. when rp# is at v hh , the boot block is unlocked and can be programmed or erased. this overrides any control from the wp# input.
2-mbit smartvoltage boot block family e 12 see new design recommendations table 2. 28f200/002 pin descriptions symbol type name and function wp# input write protect: provides a method for unlocking the boot block in a system without a 12 v supply. when wp# is at logic low, the boot block is locked , preventing program and erase operations to the boot block. if a program or erase operation is attempted on the boot block when wp# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the status register to indicate the operation failed. when wp# is at logic high, the boot block is unlocked and can be programmed or erased. note: this feature is overridden and the boot block unlocked when rp# is at v hh . see section 3.4 for details on write protection. byte# input byte# enable: not available on 28f002b . controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16). byte# pin must be controlled at cmos levels to meet the cmos current specification in the standby mode. when byte# is at logic low, the byte-wide mode is enabled , where data is read and programmed on dq 0 Cdq 7 and dq 15 /a C1 becomes the lowest order address that decodes between the upper and lower byte. dq 8 Cdq 14 are tri-stated during the byte-wide mode. when byte# is at logic high, the word-wide mode is enabled , where data is read and programmed on dq 0 Cdq 15 . v cc device power supply: 5.0 v 10%, 3.3 v 0.3 v, 2.7 vC3.6 v (be/ce only) v pp program/erase power supply: for erasing memory array blocks or programming data in each block, a voltage either of 5 v 10% or 12 v 5% must be applied to this pin. when v pp < v pplk all blocks are locked and protected against program and erase commands. gnd ground: for all internal circuitry. nc no connect: pin may be driven or left floating.
e 2-mbit smartvoltage boot block family 13 see new design recommendations 2.0 product description 2.1 memory blocking organization this product family features an asymmetrically- blocked architecture providing system memory integration. each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. the block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. the combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. for the address locations of the blo cks, see the memory maps in figures 4 and 5. 2.1.1 one 16-kb boot block the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller- based system. the 16-kbyte (16,384 bytes) boot block is located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map to accommodate different microprocessor protocols for boot code location. this boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. the protection of the boot block is controlled using a combination of the v pp , rp#, and wp# pins, as is detailed in section 3.4. 2.1.2 two 8-kb parameter blocks the boot block architecture includes parameter blocks to facilitate stor age of frequently updated small parameters that would normally require an eeprom. by using software techniques, the byte- rewrite functionality of eeproms can be emulated. these techniques are detailed in intels application note ap-604, using intels boot block flash memory parameter blocks to replace eeprom . each boot block component contains two parameter blocks of 8 kbytes (8, 192 bytes) each. the parameter blocks are not write-protectable. 2.1.3 one 96-kb + one 128-kb main block after the allocation of address space to the boot and parameter blo cks, the remai nder is divided into main blocks for data or c ode storage. each 2-mbit device contains one 96-kbyte (98,304 byte) block and one 128-kbyte (131,072 byte) block. see the memory maps for each device for more information.
2-mbit smartvoltage boot block family e 14 see new design recommendations 28f200-b 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 00000h 0ffffh 10000h 1bfffh 1c000h 1cfffh 1d000h 1dfffh 1e000h 1ffffh 28f200-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 0530_07 note: in x8 operation, the least significant system address should be connected to a -1 . memory maps are shown for x16 operation. figure 7. word-wide x16-mode memory maps 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 3ffffh 20000h 1ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 00000h 1ffffh 20000h 37fffh 38000h 39fffh 3a000h 3bfffh 3c000h 3ffffh 28f002-t 28f002-b 0530_08 note: these memory maps apply to the 28f002b or the 28f200 in x8 mode. figure 8. byte-wide x8-mode memory maps
e 2-mbit smartvoltage boot block family 15 see new design recommendations 3.0 product family principles of operation flash memory combines eprom functionality with in-circuit electrical program and erase. the boot block flash family utilizes a command user interface (cui) and automated algorithms to simplify program and erase operations. the cui allows for 100% ttl-level control inputs, fixed power supplies during erasure and programming, and maximum eprom compatibility. when v pp < v pplk , the device will only successfully execute the following commands: read array, read status register, clear status register and intelligent identifier mode. the device provides standard eprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the cui or through the standard eprom a 9 high voltage access (v id ) for prom programming equipment. the same eprom read, standby and output disable functions are available when 5 v or 12 v is applied to the v pp pin. in addition, 5 v or 12 v on v pp allows program and erase of the device. all functions associated with altering memory contents: program and erase, intelligent identifier read, and read status are accessed via the cui. the internal write state machine (wsm) completely automates program and erase, beginning operation signaled by the cui and reporting status through the status register. the cui handles the we# interface to the data and address latches, as well as system status requests during wsm operation. 3.1 bus operations flash memory reads, erases and programs in- system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. these bus operations are summarized in tables 3 and 4. 3.2 read operations 3.2.1 read array when rp# transitions from v il (reset) to v ih , the device will be in the read array mode and will respond to the read control inputs (ce#, address inputs, and oe#) without any commands being written to the cui. when the device is in the read array mode, five control signals must be controlled to obtain data at the outputs. rp# must be logic high (v ih ) we# must be logic high (v ih ) byte# must be logic high or logic low ce# must be logic low (v il ) oe must be logic low (v il ) in addition, the address of the desired location must be applied to the address pins. refer to figures 15 and 16 for the exact sequence and timing of these signals. if the device is not in read array mode, as would be the case after a program or erase operation, the read mode command (ffh) must be written to the cui before reads can take place. during system design, consideration s hould be taken to ensure address and control inputs meet required input slew rates of <10 ns as defined in figures 12 and 13.
2-mbit smartvoltage boot block family e 16 see new design recommendations table 3. bus operations for word-wide mode (byte# = v ih ) mode notes rp# ce# oe# we# a 9 a 0 v pp dq 0 C15 read 1,2,3 v ih v il v il v ih xxx d out output disable v ih v il v ih v ih x x x high z standby v ih v ih xxxxx high z deep power-down 9 v il xxxxxx high z intelligent identifier (mfr) 4v ih v il v il v ih v id v il x 0089 h intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x see table 5 write 6,7,8 v ih v il v ih v il xxx d in table 4. bus operations for byte-wide mode (byte# = v il ) mode notes rp# ce# oe# we# a 9 a 0 a C1 v pp dq 0C7 dq 8C14 read 1,2,3 v ih v il v il v ih xxxxd out high z output disable v ih v il v ih v ih xxxx high z high z standby v ih v ih xxxxxx high z high z deep power- down 9v il xxxxxxx high z high z intelligent identifier (mfr) 4v ih v il v il v ih v id v il x x 89h high z intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x x see table 5 high z write 6,7,8 v ih v il v ih v il xxxxd in high z notes: 1. refer to dc characteristics . 2. x can be v il , v ih for control pins and addresses, v pplk or v pph for v pp . 3. see dc characteristics for v pplk , v pph1 , v pph2 , v hh , v id voltages. 4. manufacturer and device codes may also be accessed via a cui write sequence, a 1 Ca 16 = x, a 1 Ca 17 = x. 5. see table 5 for device ids. 6. refer to table 7 for valid d in during a write operation. 7. command writes for block erase or word/byte program are only executed when v pp = v pph1 or v pph2 . 8. to program or erase the boot block, hold rp# at v hh or wp# at v ih . see section 3.4. 9. rp# must be at gnd 0.2 v to meet the maximum deep power-down current specified.
e 2-mbit smartvoltage boot block family 17 see new design recommendations 3.2.2 intelligent identifiers to read the manufacturer and device codes, the device must be in intelligent identifier read mode, which can be reached using two methods: by writing the intelligent identifier command (90h) or by taking the a 9 pin to v id . once in intelligent identifier read mode, a 0 = 0 outputs the manu- facturers identification code and a 0 = 1 outputs the device code. in byte-wide mode, only the lower byte of the above signatures is read (dq 15 /a C1 is a dont care in this mode). see table 5 for product signatures. to return to read array mode, write a read array command (ffh). table 5. intelligent identifier table product mfr. id device id -t (top boot) -b (bottom boot) 28f200 0089 h 2274 h 2275 h 28f002 89 h 7c h 7d h 3.3 write operations 3.3.1 command user interface (cui) the command user interface (cui) is the interface between the microprocessor and the internal chip controller. commands are written to the cui using standard microprocessor write timings. the available commands are read array, read intelligent identifier, read status register, clear status register, erase and program (summarized in tables 6 and 7). the three read modes are read array, intelligent identifier read, and status register read. for program or erase commands, the cui informs the write state machine (wsm) that a program or erase has been requested. during the execution of a program command, the wsm will control the programming sequences and the cui will only respond to status reads. during an erase cycle, the cui will respond to status reads and erase suspend. after the wsm has completed its task, it will set the wsm status bit to a 1 (ready), which indicates that the cui can respond to its full command set. note that after the wsm has returned control to the cui, the cui will stay in the current command state until it receives another command. 3.3.1.1 command function description device operations are selected by writing specific commands into the cui. tables 6 and 7 define the available commands.
2-mbit smartvoltage boot block family e 18 see new design recommendations table 6. command codes and descriptions code device mode description 00 invalid/ reserved unassigned commands that should not be used. intel reserves the right to redefine these codes for future functions. ff read array places the device in read array mode, so that array data will be output on the data pins. 40 program set-up sets the cui into a state such that the next write will latch the address and data registers on the rising edge and begin the program algorithm. the device then defaults to the read status mode, where the device outputs status register data when oe# is enabled. to read the array, issue a read array command. to cancel a program operation after issuing a program set-up command, write all 1s (ffh for x8, ffffh for x16) to the cui. this will return to read status register mode after a standard program time without modifying array contents. if a program operation has already been initiated to the wsm this command cannot cancel that operation in progress. 10 alternate prog set-up (see 40h/program set-up) 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will set both the program status (sr.4) and erase status (sr.5) bits of the status register to a 1, place the device into the read status register state, and wait for another command without modifying array contents. this can be used to cancel an erase operation after the erase set-up command has been issued. if an operation has already been initiated to the wsm this can not cancel that operation in progress. d0 erase resume/ erase confirm if the previous command was an erase set-up command, then the cui will latch address and data, and begin erasing the block indicated on the address pins. during erase, the device will respond only to the read status register and erase suspend commands and will output status register data when oe# is toggled low. status register data is updated by toggling either oe# or ce# low. b0 erase suspend valid only while an erase operation is in progress and will be ignored in any other circumstance. issuing this command will begin to suspend erase operation. the status register will indicate when the device reaches erase suspend mode. in this mode, the cui will respond only to the read array, read status register, and erase resume commands and the wsm will also set the wsm status bit to a 1 (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input control pins except rp#, which will immediately shut down the wsm and the remainder of the chip, if it is made active. during a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path. see section 3.3.4.1. 70 read status register puts the device into the read status register mode, so that reading the device outputs status register data, regardless of the address presented to the device. the device automatically enters this mode after program or erase has completed. this is one of the two commands that is executable while the wsm is operating. see section 3.3.2.
e 2-mbit smartvoltage boot block family 19 see new design recommendations table 6. command codes and descriptions (continued) code device mode description 50 clear status register the wsm can only set the program status and erase status bits in the status register to 1; it cannot clear them to 0. the status register operates in this fashion for two reasons. the first is to give the host cpu the flexibility to read the status bits at any time. second, when programming a string of bytes, a single status register query after programming the string may be more efficient, since it will return the accumulated error status of the entire string. see section 3.3.2.1. 90 intelligent identifier puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes. (a 0 = 0 for manufacturer, a 0 = 1 for device, all other address inputs are ignored). see section 3.2.2. table 7. command bus definitions first bus cycle (1) second bus cycle (1) command note oper addr data oper addr data read array 1 write x ffh intelligent identifier 1, 2, 4 write x 90h read ia iid read status register 3 write x 70h read x srd clear status register write x 50h word/byte program 1, 6, 7 write pa 40h/10h write pa pd block erase/confirm 1, 5 write ba 20h write ba d0h erase suspend write x b0h erase resume write x d0h address data ba= block address srd= status register data ia= identifier address iid= identifier data pa= program address pd= program data x= dont care notes: 1. bus operations are defined in tables 3 and 4. 2. ia = identifier address: a 0 = 0 for manufacturer code, a 0 = 1 for device code. 3. srd = data read from status register. 4. iid = intelligent identifier data. following the intelligent identifier command, two read operations access manufacturer and device codes. 5. ba = address within the block being erased. 6. pa = address to be programmed. pd = data to be programmed at location pa. 7. either 40h or 10h commands is valid. 8. when writing commands to the device, the upper data bus [dq 8 Cdq 15 ] = x (28f200 only) which is either v il or v ih , to minimize current draw.
2-mbit smartvoltage boot block family e 20 see new design recommendations table 8. status register bit definition wsms ess es dws vpps r r r 76543210 notes: sr.7 = write state machine status 1 = ready (wsms) 0 = busy check write state machine bit first to determine word/byte program or block erase completion, before checking program or erase status bits. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase when this bit is set to 1, wsm has applied the max number of erase pulses to the block and is still unable to verify successful block erasure. sr.4 = program status (dws) 1 = error in byte/word program 0 = successful byte/word program when this bit is set to 1, wsm has attempted but failed to program a byte or word. sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered, and informs the system if v pp has not been switched on. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pph . sr.2Csr.0 = reserved for future enhancements (r) these bits are reserved for future use and should be masked out when polling the status register. 3.3.2 status register the device status register indicates when a program or erase operation is complete, and the success or failure of that operation. to read the status register write the read status (70h) command to the cui. this causes all subsequent read operations to output data from the status register until another command is written to the cui. to return to reading from the array, issue a read array (ffh) command. the status register bits are output on dq 0 Cdq 7 , in both byte-wide (x8) or word-wide (x16) mode. in the word-wide mode the upper byte, dq 8 Cdq 15 , outputs 00h during a read status command. in the byte-wide mode, dq 8 Cdq 14 are tri-stated and dq 15 /a C1 retains the low order address function. important: the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs last in the read cycle. this prevents possible bus errors which might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, the sr.7 register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation.
e 2-mbit smartvoltage boot block family 21 see new design recommendations 3.3.2.1 clearing the status register the wsm sets status bits 3 through 7 to 1, and clears bits 6 and 7 to 0, but cannot clear status bits 3 through 5 to 0. bits 3 through 5 can only be cleared by the controlling cpu through the use of the clear status register (50h) command, because these bits indicate various error conditions. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in s equence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note, again, that a read array command must be issued before data can be read from the memory or intelligent identifier. 3.3.3 program mode programming is executed using a two-write sequence. the program set-up command is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to: 1. program the desired bits of the addressed memory word or byte. 2. verify that the desired bits are sufficiently programmed. programming of the memory results in specific bits within a byte or word being changed to a 0. if the user attempts to program 1s, there will be no change of the memory cell content and no error occurs. the status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a 0. the status register can be polled by toggling either ce# or oe#. while programming, the only valid command is read status register. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit 4 of the status register is set to a 1 to indicate a program failure. if bit 3 is set to a 1, then v pp was not within acceptable limits, and the wsm did not execute the programming sequence. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, reads from the memory array or intelligent identifier cannot be accomplished until the cui is given the appropriate command. 3.3.4 erase mode to erase a block, write the erase set-up and erase confirm commands to the cui, along with the addresses identifying the block to be erased. these addresses are latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. only one block can be erased at a time. the wsm will execute a sequence of internally timed events to: 1. program all bits within the block to 0. 2. verify that all bits within the block are sufficiently programmed to 0. 3. erase all bits within the block to 1. 4. verify that all bits within the block are sufficiently erased. while the erase sequence is executing, bit 7 of the status register is a 0. when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, bit 5 of the status register will be set to a 1, indicating an erase failure. if v pp was not within acceptable limits after the erase confirm command is issued, the wsm will not execute an erase sequence; instead, bit 5 of the status register is set to a 1 to indicate an erase failure, and bit 3 is set to a 1 to identify that v pp supply voltage was not within acceptable limits. clear the status register before attempting the next operation. any cui instruction can follow after erasure is completed; however, reads from the memory array, status register, or intelligent identifier cannot be accomplished until the cui is given the read array command.
2-mbit smartvoltage boot block family e 22 see new design recommendations 3.3.4.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase-sequence interruption in order to read data from another block of the memory. once the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pause the erase sequence at a predetermined point in the erase algorithm. the status register will indicate if/when the erase operation has been suspended. at this point, a read array command can be written to the cui in order to read data from blo cks other than that which is being suspended. the only other valid command at this time is the erase resume command or read status register command. during erase suspend mode, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. to resume the erase operation, enable the chip by taking ce# to v il , then issuing the erase resume command, which continues the erase sequence to completion. as with the end of a standard erase operation, the status register must be read, cleared, and the next instruction issued in order to continue. 3.4 boot block locking the boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blo cks are programmed and erased independently as necessary. only the boot block can be locked independently from the other blocks. the truth table, table 9, clearly defines the write protection methods. 3.4.1 v pp = v il for complete protection for complete write protection of all blocks in the flash device, the v pp programming voltage can be held low. when v pp is below v pplk , any program or erase operation will result in a error in the status register. 3.4.2 wp# = v il for boot block locking when wp# = v il , the boot block is locked and any program or erase operation to the boot block will result in an error in the status register. all other blocks remain unlocked in this c ondition and can be programmed or erased normally. note that this feature is overridden and the boot block unlocked when rp# = v hh . 3.4.3 rp# = v hh or wp# = v ih for boot block unlocking two methods can be used to unlock the boot block: 1. wp# = v ih 2. rp# = v hh if both or either of these two conditions are met, the boot block will be unlocked and can be programmed or erased. 3.4.4 upgrade note for 8-mbit 44-psop package if upgradability to 8 mbit is required, note that the 8-mbit in the 44-psop does not have a wp# because no pins were available for the 8-mbit upgrade address. thus, in this density-package combination only, v hh (12 v) on rp# is required to unlock the boot block. unlocking with a logic-level signal is not possible. if this functionality is required, and 12 v is not available, consider using the 48-tsop package, which has a wp# pin and can be unlocked with a logic-level signal. all other density-package combinations have wp# pins. table 9. write protection truth table v pp rp# wp# write protection provided v il x x all blocks locked 3 v pplk v il x all blocks locked (reset) 3 v pplk v hh x all blocks unlocked 3 v pplk v ih v il boot block locked 3 v pplk v ih v ih all blocks unlocked
e 2-mbit smartvoltage boot block family 23 see new design recommendations sr.7 = 1 ? no yes start write 40h, word/byte address write word/byte data/address full status check if desired word/byte program complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error bus operation command comments standby standby check sr.3 1 = v pp low detect sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write setup program data = data to program addr = location to program read data = 40h addr = word/byte to program check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent word/byte program operations. sr full status check can be done after each word/byte program, or after a sequence of word/byte programs. write ffh after the last program operation to reset device to read array mode. standby sr.3 = sr.4 = word/byte program error word/byte program successful check sr.4 1 = word/byte program error program status register data toggle ce# or oe# to update srd 0530_09 figure 9. automated word/byte programming flowchart
2-mbit smartvoltage boot block family e 24 see new design recommendations sr.7 = 0 1 start write 20h, block address write d0h and block address full status check if desired block erase complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error suspend erase suspend erase loop yes no 1 0 command sequence error sr.3 = sr.5 = sr.4,5 = block erase error bus operation command comments standby check sr.4,5 both 1 = command sequence error standby check sr.3 1 = v pp low detect sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erase before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1 = block erase error standby bus operation command comments write write erase setup read data = 20h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to reset device to read array mode. status register data toggle ce# or oe# to update status register standby erase confirm data = d0h addr = within block to be erased block erase successful 0530_10 figure 10. automated block erase flowchart
e 2-mbit smartvoltage boot block family 25 see new design recommendations start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh read array data erase completed done reading yes write ffh write d0h erase resumed read array data 0 1 read array data from block other than the one being programmed. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = x bus operation write write read read standby standby write command program suspend read array program resume 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write write read read standby standby write data=70h addr=x command program suspend read array program resume erase suspend read status read array erase resume 0530_11 figure 11. erase suspend/resume flowchart
2-mbit smartvoltage boot block family e 26 see new design recommendations 3.5 power consumption 3.5.1 active power with ce# at a logic-low level and rp# at a logic- high level, the device is placed in the active mode. refer to the dc characteristics table for i cc current values. 3.5.2 automatic power savings (aps) automatic power savings (aps) provides low- power operation during active mode. power reduction control (prc) circuitry allows the device to put itself into a low current state when not being accessed. after data is read from the memory array, prc logic controls the devices power consumption by entering the aps mode where typical i cc current is less than 1 ma. the device stays in this static state with outputs valid until a new location is read. 3.5.3 standby power with ce# at a logic-high level (v ih ), and the cui in read mode, the memory is placed in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs (dq 0 Cdq 15 or dq 0 Cdq 7 ) are placed in a high- impedance state independent of the status of the oe# signal. when ce# is at logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. 3.5.4 deep power-down mode the smartvoltage boot block family supports a low typical i cc in deep power-down mode, which turns off all circuits to save power. this mode is activated by the rp# pin when it is at a logic-low (gnd 0.2 v). note note: byte# pin must be at cmos levels to meet the i ccd specification. during read modes, the rp# pin going low de- selects the memory and places the output drivers in a high impedance state. recovery from the deep power-down state, requires a minimum access time of t phqv (see ac characteristics table). during erase or program modes, rp# low will abort either erase or program operations, but the memory contents are no longer valid as the data has been corrupted by the rp# function. as in the read mode above, all internal circuitry is turned off to achieve the power savings. rp# transitions to v il , or turning power off to the device will clear the status register. 3.6 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp or v cc , powers-up first. the cui is reset to the read mode after power-up, but the system must drop ce# low or present a new address to ensure valid data at the outputs. a system desi gner must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powerg ood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.1 rp# connected to system reset the use of rp# during system reset is important with automated program/erase devices because the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization would not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper cpu initialization following a system reset by connecting the rp# pin to the same reset# signal that resets the system cpu.
e 2-mbit smartvoltage boot block family 27 see new design recommendations 3.6.2 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode, or after v cc transitions above v lko (lockout voltage), is read array mode. after any word/byte program or block erase operation is complete and even after v pp transitions down to v pplk , the cui must be reset to read array mode via the read array command if accesses to the flash memory are desired. please refer to intels application note ap-617 additional flash data protection using v pp , rp#, and wp# for a circuit-level description of how to implement the protection discussed in section 3.6. 3.7 power supply decoupling flash memorys power switching characteristics require careful device decoupling methods. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. active current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 v pp trace on printed circuit boards designing for in-system programming of the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. one should use similar trace widths and layout considerations given to the v cc power supply trace. adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. note: table headings in the dc and ac characteristics tables (i.e., bv-60, bv-80, bv-120, tbv-80, tbe- 120) refer to the specific products listed below. see section 5.0 for more information on product naming and line items. abbreviation applicable product names bv-60 e28f002bv-t60, e28f002bv-b60, pa28f200bv-t60, pa28f200bv-b60, e28f200cv-t60, e28F200CV-B60, e28f200bv-t60, e28f200bv-b60 bv-80 e28f002bv-t80, e28f002bv-b80, pa28f200bv-t80, pa28f200bv-b80, e28f200cv-t80, e28F200CV-B80, e28f200bv-t80, e28f200bv-b80 bv-120 e28f002bv-t120, e28f002bv-b120, pa28f200bv-t120, pa28f200bv-b120 tbv-80 te28f002bv-t80, te28f002bv-b80, tb28f200bv-t80, tb28f200bv-b80, te28f200cv-t80, te28F200CV-B80, te28f200bv-t80, te28f200bv-b80
2-mbit smartvoltage boot block family e 28 see new design recommendations 4.0 electrical specifications 4.1 absolute maximum ratings* commercial operating temperature during read .............................. 0 c to +70 c during block erase and word/byte program ............ 0 c to +70 c temperature under bias ....... C10 c to +80 c extended operating temperature during read .......................... C40 c to +85 c during block erase and word/byte program ........ C40 c to +85 c temperature under bias ....... C40 c to +85 c storage temperature................. C65 c to +125 c voltage on any pin (except v cc , v pp , a 9 and rp#) with respect to gnd ........... C2.0 v to +7.0 v (2) voltage on pin rp# or pin a 9 with respect to gnd ....... C2.0 v to +13.5 v (2,3) v pp program voltage with respect to gnd during block erase and word/byte program .. C2.0 v to +14.0 v (2,3) v cc supply voltage with respect to gnd ........... C2.0 v to +7.0 v (2) output short circuit current....................100 ma (4) notice: this datasheet contains preliminary information on new products in production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is C0.5 v on input/output pins. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 0.5 v which, during transitions, may overshoot to v cc + 2.0 v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. maximum dc voltage on rp# or a 9 may overshoot to 13.5 v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 4.2 commercial operating conditions table 10. commercial temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature 0 +70 c v cc 3.3 v v cc supply voltage ( 0.3 v) 3.0 3.6 volts 5 v v cc supply voltage (10%) 1 4.50 5.50 volts 5 v v cc supply voltage (5%) 2 4.75 5.25 volts notes: 1. 10% v cc specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration. 2. 5% v cc specifications apply to the 60 ns version in its high-speed test configuration.
e 2-mbit smartvoltage boot block family 29 see new design recommendations 4.2.1 applying v cc voltages when applying v cc voltage to the device, a delay may be required before initiating device operation, depending on the v cc ramp rate. if v cc ramps slower than 1v/100 s (0.01 v/s) then no delay is required. if v cc ramps faster than 1v/100 s (0.01 v/s), then a delay of 2 s is required before initiating device operation. rp# = gnd is recommended during power-up to protect against spurious write signals when v cc is between v lko and v ccmin . v cc ramp rate required timing 1v/100 m s no delay required. > 1v/100 m s a delay time of 2 m s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. this delay is measured beginning from the time v cc reaches v ccmin (3.0 v for 3.3 0.3 v operation; and 4.5 v for 5 v operation). notes: 1. these requirements must be strictly followed to guarantee all other read and write specifications. 2. to switch between 3.3 v and 5 v operation, the system should first transition v cc from the existing voltage range to gnd, and then to the new voltage. any time the v cc supply drops below v ccmin , the chip may be reset, aborting any operations pending or in progress. 3. these guidelines must be followed for any v cc transition from gnd. 4.3 capacitance t a = 25 c, f = 1 mhz symbol parameter note typ max unit conditions c in input capacitance 1 6 8 pf v in = 0 v c out output capacitance 1, 2 10 12 pf v out = 0 v notes: 1. sampled, not 100% tested. 2. for the 28f002b, address pin a 10 follows the c out capacitance numbers.
2-mbit smartvoltage boot block family e 30 see new design recommendations 4.4 dc characteristics commercial prod bv-60 bv-80 bv-120 sym parameter v cc 3.3 0.3 v 5 v 10% unit test conditions note typ max typ max i il input load current 1 1.0 1.0 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3 0.4 1.5 0.8 2.0 ma v cc = v cc max ce# = rp# = byte# = wp# = v ih 60 110 50 130 a v cc = v cc max ce# = rp# = v cc 0.2 v i ccd v cc deep power-down current 1 0.2 8 0.2 8 a v cc = v cc max v in = v cc or gnd rp# = gnd 0.2 v i ccr v cc read current for word or byte 1,5,6 15 30 50 60 ma cmos inputs v cc = v cc max ce# = gnd, oe# = v cc f = 10 mhz (5 v), 5 mhz (3.3 v) i out = 0 ma, inputs = gnd 0.2 v or v cc 0.2 v 15 30 55 65 ma ttl inputs v cc = v cc max ce# = v il , oe# = v ih f = 10 mhz (5 v), 5 mhz (3.3 v) i out = 0 ma, inputs = v il or v ih i ccw v cc program current for word or byte 1,4 13 30 30 50 ma v pp = v pph 1 (at 5 v) program in progress 10 25 30 45 ma v pp = v pph 2 (at 12 v) program in progress i cce v cc erase current 1,4 13 30 18 35 ma v pp = v pph 1 (at 5 v) block erase in progress 10 25 18 30 ma v pp = v pph 2 (at 12 v) block erase in progress
e 2-mbit smartvoltage boot block family 31 see new design recommendations 4.4 dc characteristics commercial (continued) prod bv-60 bv-80 bv-120 sym parameter v cc 3.3 0.3 v 5 v 10% unit test conditions note typ max typ max i cces v cc erase suspend current 1,2 3 8.0 5 10 ma ce# = v ih block erase suspend i pps v pp standby current 1 0.5 15 0.5 10 a v pp < v pph 2 i ppd v pp deep power-down current 1 0.2 5.0 0.2 5.0 a rp# = gnd 0.2 v i ppr v pp read current 1 50 200 30 200 a v pp 3 v pph 2 i ppw v pp program current for word or byte 1,4 13 30 13 25 ma v pp = v pph 1 (at 5 v) program in progress 825820 v pp = v pph 2 (at 12 v) program in progress i ppe v pp erase current 1,4 13 30 10 20 ma v pp = v pph 1 (at 5 v) block erase in progress 825515 v pp = v pph 2 (at 12 v) block erase in progress i ppes v pp erase suspend current 1 50 200 30 200 a v pp = v pph block erase suspend in progress i rp# rp# boot block unlock current 1,4 500 500 a rp# = v hh i id a 9 intelligent identifier current 1,4 500 500 a a 9 = v id
2-mbit smartvoltage boot block family e 32 see new design recommendations 4.4 dc characteristics commercial (continued) prod bv-60 bv-80 bv-120 sym parameter v cc 3.3 0.3 v 5 v 10% unit test conditions note min max min max v id a 9 intelligent identifier voltage 11.4 12.6 11.4 12.6 v v il input low voltage C0.5 0.8 C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5v 2.0 v cc + 0.5v v v ol output low voltage 0.45 0.45 v v cc = v cc min i ol = 5.8 ma v oh 1 output high voltage (ttl) 2.4 2.4 v v cc = v cc min i oh = C2.5 ma v oh 2 output high voltage (cmos) 0.85 v cc 0.85 v cc v v cc = v cc min i oh = C2.5 ma v cc C 0.4v v cc C 0.4v v v cc = v cc min i oh = C100 m a v pplk v pp lock-out voltage 3 0.0 1.5 0.0 1.5 v total write protect v pph 1v pp (prog/erase operations) 4.5 5.5 4.5 5.5 v v pp at 5 v v pph 2v pp (prog/erase operations) 11.4 12.6 11.4 12.6 v v pp at 12 v v lko v cc erase/prog lock voltage 8 2.0 2.0 v v hh rp# unlock voltage 11.4 12.6 11.4 12.6 v boot block unlock notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, t = +25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and word/byte programs are inhibited when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 7. for the 28f002b, address pin a 10 follows the c out capacitance numbers. 8. for all bv/cv parts, v lko = 2.0 v for both 3.3 v and 5 v operations.
e 2-mbit smartvoltage boot block family 33 see new design recommendations test points input output 1.5 3.0 0.0 1.5 note: ac test inputs are driven at 3.0 v for a logic 1 and 0.0 v for a logic 0. input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) <10 ns. 0530_12 figure 12. 3.3 v inputs and measurement points test points input output 2.0 0.8 0.8 2.0 2.4 0.45 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic 1 and v ol (0.45 v ttl ) for a logic 0. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ) . output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. 0530_13 figure 13. 5 v inputs and measurement points c l out v cc device under test r 1 r 2 0530_14 note: see table for component values. figure 14. test configuration test configuration component values test configuration c l (pf) r 1 ( w )r 2 ( w ) 3.3 v standard test 50 990 770 5 v standard test 100 580 390 5 v high-speed test 30 580 390 note: c l includes jig capacitance.
2-mbit smartvoltage boot block family e 34 see new design recommendations 4.5 ac characteristics commercial prod bv-60 sym parameter v cc 3.3 0.3 v (5) 5 v 5% (6) 5 v 10% (7) unit load 50 pf 30 pf 100 pf note min max min max min max t avav read cycle time 110 60 70 ns t avqv address to output delay 110 60 70 ns t elqv ce# to output delay 2 110 60 70 ns t phqv rp# to output delay 0.8 0.45 0.45 m s t glqv oe# to output delay 2 65 30 35 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# to output in high z 3 45 20 20 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# to output in high z 3 45 20 20 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 3000ns t elfl t elfh ce# low to byte# high or low 3000ns t avfl address to byte# high or low 3555ns t flqv t fhqv byte# to output delay 3,4 110 60 70 ns t flqz byte# low to output in high z 3452025ns t plph reset pulse width low 8 150 60 60 ns t plqz rp# low to output high-z 150 60 60 ns
e 2-mbit smartvoltage boot block family 35 see new design recommendations 4.5 ac characteristics commercial (continued) prod bv-80 bv-120 sym parameter v cc 3.3 0.3v (5) 5v 10% (7) 3.3 0.3v (5) 5v 10% (7) unit load 50 pf 100 pf 50 pf 100 pf notes min max min max min max min max t avav read cycle time 150 80 180 120 ns t avqv address to output delay 150 80 180 120 ns t elqv ce# to output delay 2 150 80 180 120 ns t phqv rp# to output delay 0.8 0.45 0.8 0.45 m s t glqv oe# to output delay 2 90 40 90 40 ns t elqx ce# to output in low z 3 0 0 0 0 ns t ehqz ce# to output in high z 3 45 20 45 25 ns t glqx oe# to output in low z 3 0 0 0 0 ns t ghqz oe# to output in high z 3 45 20 45 20 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 0 0 ns t elfl t elfh ce# low to byte# high or low 30 0 0 0 ns t avfl address to byte# high or low 35555ns t flqv t fhqv byte# to output delay 3,4 150 80 180 120 ns t flqz byte# low to output in high z 3 60306030ns t plph reset pulse width low 8 150 60 150 60 ns t plqz rp# low to output high-z 150 60 150 60 ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce Ct oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. t flqv , byte# switching low to valid output delay will be equal to t avqv , measured from the time dq 15 /a C1 becomes valid. 5. see test configuration (figure 14), 3.3 v standard test component values. 6. see test configuration (figure 14), 5 v high-speed test component values. 7. see test configuration (figure 14), 5 v standard test component values. 8. the specification t plph is the minimum time that rp# must be held low in order to product a valid reset of the device.
2-mbit smartvoltage boot block family e 36 see new design recommendations address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v phqv t high z valid output data valid standby avav t ehqz t ghqz t oh t glqv t glqx t elqv t elqx t avqv t high z 0530_15 figure 15. ac waveforms for read operations address stable device address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) byte# (f) data (d/q) (dq0-dq7) ol v oh v high z data output on dq0-dq7 data valid standby avav t ehqz t ghqz t avqv t high z glqv t elqv t avqv t oh t data output on dq0-dq7 data (d/q) (dq8-dq14) ol v oh v high z data output on dq8-dq14 high z (dq15/a-1) ol v oh v high z high z data output on dq15 address input flqz t elqx t elfl t avfl t glqx t 0530_16 figure 16. byte# timing diagram for read operations
e 2-mbit smartvoltage boot block family 37 see new design recommendations 4.6 ac characteristics we#-controlled write operations (1) commercial prod bv-60 sym parameter v cc 3.3 0.3 v (9) 5 v 5% (10) 5 v 10% (10) unit load 50 pf 30 pf 100 pf note min max min max min max t avav write cycle time 110 60 70 ns t phwl rp# setup to we# going low 0.8 0.45 0.45 m s t elwl ce# setup to we# going low 0 0 0 ns t phhwh boot block lock setup to we# going high 6,8 200 100 100 ns t vpwh v pp setup to we# going high 5,8 200 100 100 ns t avwh address setup to we# going high 3905050ns t dvwh data setup to we# going high 4 90 50 50 ns t wlwh we# pulse width 90 50 50 ns t whdx data hold time from we# high 4 0 0 0 ns t whax address hold time from we# high 3000ns t wheh ce# hold time from we# high 0 0 0 ns t whwl we# pulse width high 20 10 20 ns t whqv1 duration of word/byte program 2,5 6 6 6 s t whqv2 duration of erase (boot) 2,5,6 0.3 0.3 0.3 s t whqv3 duration of erase (parameter) 2,5 0.3 0.3 0.3 s t whqv4 duration of erase (main) 2,5 0.6 0.6 0.6 s t qvvl v pp hold from valid srd 5,8 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 ns t phbr boot-block lock delay 7,8 200 100 100 ns
2-mbit smartvoltage boot block family e 38 see new design recommendations 4.6 ac characteristics we#-controlled write operations (1) commercial (continued) prod bv-80 bv-120 sym parameter v cc 3.3 0.3v (9) 5v10% (11) 3.3 0.3v (9) 5v10% (11) unit load 50 pf 100 pf 50 pf 100 pf notes min max min max min max min max t avav write cycle time 150 80 180 120 ns t phwl rp# setup to we# going low 0.8 0.45 0.8 0.45 m s t elwl ce# setup to we# going low 0000ns t phhwh boot block lock setup to we# going high 6,8 200 100 200 100 ns t vpwh v pp setup to we# going high 5,8 200 100 200 100 ns t avwh address setup to we# going high 3 120 50 150 50 ns t dvwh data setup to we# going high 4 120 50 150 50 ns t wlwh we# pulse width 120 50 150 50 ns t whdx data hold time from we# high 40 0 0 0 ns t whax address hold time from we# high 30 0 0 0 ns t wheh ce# hold time from we# high 0000ns t whwl we# pulse width high 30 30 30 30 ns t whqv1 word/byte program time 2,5 6 6 6 6 s t whqv2 erase duration (boot) 2,5,6 0.3 0.3 0.3 0.3 s t whqv3 erase duration (param) 2,5 0.3 0.3 0.3 0.3 s t whqv4 erase duration (main) 2,5 0.6 0.6 0.6 0.6 s t qvvl v pp hold from valid srd 5,8 0 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 0 ns t phbr boot-block lock delay 7,8 200 100 200 100 ns
e 2-mbit smartvoltage boot block family 39 see new design recommendations notes: 1. read timing characteristics during program and erase operations are the same as during read-only operations. r efer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. refer to command definition table for valid a in . (table 7) 4. refer to command definition table for valid d in . (table 7) 5. program/erase durations are measured to valid srd data (successful operation, sr.7 = 1). 6. for boot block program/erase, rp# should be held at v hh or wp# should be held at v ih until operation completes successfully. 7. time t phbr is required for successful locking of the boot block. 8. sampled, but not 100% tested. 9. see test configuration (figure 14), 3.3 v standard test component values. 10. see test configuration (figure 14), 5 v high-speed test component values. 11. see test configuration (figure 14), 5 v standard test component values. addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v il v in d in a in a wheh t whwl t valid srd in d whqv1,2,3,4 t phhwh t ih v phwl t high z whdx t ih v il v v (v) pp 12 3 4 6 5 pph v pplk v pph v1 2 wp# il v ih v avav t avwh t whax t dvwh t wlwh t qvph t qvvl t vpwh t in d elwl t notes: 1. v cc power-up and standby. 2. write program or erase set-up command. 3. write valid address and data (program) or erase confirm command. 4. automated program or erase delay. 5. read status register data. 6. write read array command. 0530_17 figure 17. ac waveforms for write operations (we# Ccontrolled writes)
2-mbit smartvoltage boot block family e 40 see new design recommendations 4.7 ac characteristics ce#-controlled write operations (1, 12) commercial prod bv-60 sym parameter v cc 3.3 0.3 v (9) 5 v 5% (10) 5 v 10% (11) unit load 50 pf 30 pf 100 pf note min max min max min max t avav write cycle time 110 60 70 ns t phel rp# high recovery to ce# going low 0.8 0.45 0.45 s t wlel we# setup to ce# going low 0 0 0 ns t phheh boot block lock setup to ce# going high 6,8 200 100 100 ns t vpeh v pp setup to ce# going high 5,8 200 100 100 ns t aveh address setup to ce# going high 3905050ns t dveh data setup to ce# going high 4 90 50 50 ns t eleh ce# pulse width 90 50 50 ns t ehdx data hold time from ce# high 4 0 0 0 ns t ehax address hold time from ce# high 3000ns t ehwh we # hold time from ce# high 0 0 0 ns t ehel ce# pulse width high 20 10 20 ns t ehqv1 duration of word/byte programming operation 2,5 6 6 6 s t ehqv2 erase duration (boot) 2,5,6 0.3 0.3 0.3 s t ehqv3 erase duration (param) 2,5 0.3 0.3 0.3 s t ehqv4 erase duration(main) 2,5 0.6 0.6 0.6 s t qvvl v pp hold from valid srd 5,8 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 ns t phbr boot-block lock delay 7,8 200 100 100 ns
e 2-mbit smartvoltage boot block family 41 see new design recommendations 4.7 ac characteristics ce#-controlled write operations (1, 12) commercial (continued) prod bv-80 bv-120 sym parameter v cc 3.3 0.3v (9) 5v10% (11) 3.3 0.3v (9) 5v10% (11) unit load 50 pf 100 pf 50 pf 100 pf notes min max min max min max min max t avav write cycle time 150 80 180 120 ns t phel rp# high recovery to ce# going low 0.8 0.45 0.8 0.45 m s t wlel we# setup to ce# going low 0000ns t phheh boot block lock setup to ce# going high 6,8 200 100 200 100 ns t vpeh v pp setup to ce# going high 5,8 200 100 200 100 ns t aveh address setup to ce# going high 3 120 50 150 50 ns t dveh data setup to ce# going high 4 120 50 150 50 ns t eleh ce# pulse width 120 50 150 50 ns t ehdx data hold time from ce# high 40 0 0 0 ns t ehax address hold time from ce# high 30 0 0 0 ns t ehwh we # hold time from ce# high 0000ns t ehel ce# pulse width high 30 30 30 30 ns t ehqv1 duration of word/byte programming operation 2,56666 s t ehqv2 erase duration (boot) 2,5,6 0.3 0.3 0.3 0.3 s t ehqv3 erase duration (param) 2,5 0.3 0.3 0.3 0.3 s t ehqv4 erase duration(main) 2,5 0.6 0.6 0.6 0.6 s t qvvl v pp hold from valid srd 5,8 0 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 0 ns t phbr boot-block lock delay 7,8 200 100 200 100 ns
2-mbit smartvoltage boot block family e 42 see new design recommendations notes: see ac characteristics we#-controlled write operations for notes 1 through 11. 12. chip-enable controlled writes: write operations are driven by the valid combination of ce# and we# in systems where ce# defines the write pulse-width (within a longer we# timing waveform), all set-up, hold and inactive we# times should be measured relative to the ce# waveform. addresses (a) we# (w) oe# (g) ce# (e) data (d/q) rp# (p) ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v in d in a in a avav t valid srd in d qvph t phheh t high z ehdx t ih v il v v (v) pp 12 3 4 6 5 ehax t ehqv1,2,3,4 t ehel t ehwh t eleh t dveh t vpeh t qvvl t phel t wlel t aveh t pplk v pph v1 2 pph v il v ih v il v ih v wp# in d notes: 1. v cc power-up and standby. 2. write program or erase set-up command. 3. write valid address and data (program) or erase confirm command. 4. automated program or erase delay. 5. read status register data. 6. write read array command. 0530_18 figure 18. alternate ac waveforms for write operations (ce# Ccontrolled writes)
e 2-mbit smartvoltage boot block family 43 see new design recommendations 4.8 erase and program timings commercial t a = 0 c to +70 c v pp 5 v 10% 12 v 5% v cc 3.3 0.3 v 5 v 10% 3.3 0.3 v 5 v 10% parameter typ max typ max typ max typ max unit boot/parameter block erase time 0.84 7 0.8 7 0.44 7 0.34 7 s main block erase time 2.4 14 1.9 14 1.3 14 1.1 14 s main block program time (byte) 1.7 1.8 1.6 1.2 s main block program time (word) 1.1 0.9 0.8 0.6 s byte program time 10 10 8 8 s word program time 13 13 8 8 s notes: 1. all numbers are sampled, not 100% tested. 2. max erase times are specified under worst case conditions. the max erase times are tested at the same value independent of v cc and v pp . see note 3 for typical conditions. 3. typical conditions are +25 c with v cc and v pp at the center of the specified voltage range. production programming using v cc = 5.0 v, v pp = 12.0 v typically results in a 60% reduction in programming time. 4. contact your intel representative for information regarding maximum byte/word program specifications. 4.9 extended operating conditions table 11. extended temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature C40 +85 c v cc 3.3 v v cc supply voltage ( 0.3 v) 1 3.0 3.6 volts 5 v v cc supply voltage (10%) 2 4.50 5.50 volts notes: 1. ac specifications are valid at both voltage ranges. see dc characteristics tables for voltage range-specific specifications. 2. 10% v cc specifications apply to 80 ns and 120 ns versions in their standard test configuration.
2-mbit smartvoltage boot block family e 44 see new design recommendations 4.9.1 applying v cc voltages when applying v cc voltage to the device, a delay may be required before initiating device operation, depending on the v cc ramp rate. if v cc ramps slower than 1v/100 s (0.01 v/s) then no delay is required. if v cc ramps faster than 1v/100 s (0.01 v/s), then a delay of 2 s is required before initiating device operation. rp# = gnd is recommended during power-up to protect against spurious write signals when v cc is between v lko and v ccmin . v cc ramp rate required timing 1v/100 m s no delay required. > 1v/100 m s a delay time of 2 m s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. this delay is measured beginning from the time v cc reaches v ccmin ( 3.0 v for 3.3 0.3 v operation; and 4.5 v for 5 v operation). notes: 1. these requirements must be strictly followed to guarantee all other read and write specifications. 2. to switch between 3.3 v and 5 v operation, the system should first transition v cc from the existing voltage range to gnd, and then to the new voltage. any time the v cc supply drops below v ccmin , the chip may be reset, aborting any operations pending or in progress. 3. these guidelines must be followed for any v cc transition from gnd. 4.10 capacitance t a = 25 c, f = 1 mhz symbol parameter note typ max unit conditions c in input capacitance 1 6 8 pf v in = 0v c out output capacitance 1 10 12 pf v out = 0v note: 1. sampled, not 100% tested.
e 2-mbit smartvoltage boot block family 45 see new design recommendations 4.11 dc characteristics extended temperature operations prod tbv-80 tbv-80 tbe-120 sym parameter v cc 3.3 0.3 v 5 v 10% unit test conditions notes typ max typ max i il input load current 1 1.0 1.0 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3 60 110 70 150 a cmos levels v cc = v cc max ce# = rp# = wp# = v cc 0.2 v 0.4 1.5 0.8 2.5 ma ttl levels v cc = v cc max ce# = rp# = byte# = v ih i ccd v cc deep power-down current 1 0.2 8 0.2 8 a v cc = v cc max v in = v cc or gnd rp# = gnd 0.2 v i ccr v cc read current for word or byte 1,5,6 15 30 50 65 ma cmos inputs v cc = v cc max ce = v il f = 10 mhz (5 v) 5 mhz (3.3 v) i out = 0 ma inputs = gnd 0.2 v or v cc 0.2 v 15 30 55 70 ma ttl inputs v cc = v cc max ce# = v il f = 10 mhz (5 v) 5 mhz (3.3 v) i out = 0 ma inputs = v il or v ih
2-mbit smartvoltage boot block family e 46 see new design recommendations 4.11 dc characteristics extended temperature operations (continued) prod tbv-80 tbv-80 tbe-120 sym parameter v cc 3.3 0.3 v 5 v 10% unit test conditions note typ max typ max i ccw v cc program current for word or byte 1,4 13 30 30 50 ma v pp = v pph 1 (at 5 v) program in progress 10 25 30 45 ma v pp = v pph 2 (at 12 v) program in progress i cce v cc erase current 1,4 13 30 22 45 ma v pp = v pph 1 (at 5 v) block erase in progress 10 25 18 40 ma v pp = v pph 2 (at 12 v) block erase in progress i cces v cc erase suspend current 1,2 3 8.0 5 12.0 ma ce# = v ih block erase suspend v pp = v pph 1 (at 5 v) i pps v pp standby current 1 5 15 5 15 a v pp < v pph 2 i ppd v pp deep power-down current 1 0.2 10 0.2 10 a rp# = gnd 0.2 v i ppr v pp read current 1 50 200 50 200 a v pp 3 v pph 2 i ppw v pp program current for word or byte 1,4 13 30 13 30 ma v pp = v pph 1 (at 5 v) 8 25 8 25 ma v pp = v pph 2 (at 12 v) i ppe v pp erase current 1,4 13 30 15 25 ma v pp = v pph 1 (at 5 v) block erase in progress 8251020ma v pp = v pph 2 (at 12 v) block erase in progress i ppes v pp erase suspend current 1 50 200 50 200 a v pp = v pph block erase suspend in progress i rp# rp# boot block unlock current 1,4 500 500 a rp# = v hh v pp = 12 v i id a 9 intelligent identifier current 1,4 500 500 a a 9 = v id
e 2-mbit smartvoltage boot block family 47 see new design recommendations 4.11 dc characteristics extended temperature operations (continued) prod tbv-80 tbv-80 tbe-120 sym parameter v cc 3.3 0.3 v 5 v 10% unit test conditions notes typ max typ max v id a 9 intelligent identifier voltage 11.4 12.6 11.4 12.6 v v il input low voltage C0.5 0.8 C0.5 0.8 v v ih input high voltage 2.0 v cc 0.5v 2.0 v cc 0.5v v v ol output low voltage 0.45 0.45 v v cc = v cc min i ol = 5.8 ma (5 v) 2 ma (3.3 v) v pp = 12v v oh 1 output high voltage (ttl) 2.4 2.4 v v cc = v cc min i oh = C2.5 ma v oh 2 output high voltage (cmos) 0.85 v cc 0.85 v cc v v cc = v cc min i oh = C2.5 ma v cc C 0.4v v cc C 0.4v v v cc = v cc min i oh = C100 a v pplk v pp lock-out voltage 3 0.0 1.5 0.0 1.5 v complete write protection v pph 1v pp during program/erase 4.5 5.5 4.5 5.5 v v pp at 5 v v pph 2 operations 11.4 12.6 11.4 12.6 v v pp at 12 v v lko v cc program/erase lock voltage 8 2.0 2.0 v v hh rp# unlock voltage 11.4 12.6 11.4 12.6 v v pp = 12 v boot block program/ erase
2-mbit smartvoltage boot block family e 48 see new design recommendations notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, t = +25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . 3. block erases and word/byte programs inhibited when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 7. for the 28f002b address pin a 10 follows the c out capacitance numbers. 8. for all bv/cv parts, v lko = 2.0 v for 3.3 v and 5.0 v operations. test points input output 1.5 3.0 0.0 1.5 0530_12 note: ac test inputs are driven at 3.0 v for a logic 1 and 0.0 v for a logic 0. input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) <10 ns. figure 19. 3.3 v input range and measurement points test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0530_13 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic 1 and v ol (0.45 v ttl ) for a logic 0. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. figure 20. 5 v input range and measurement points c l out v cc device under test r 1 r 2 0530_14 note: see table for component values. figure 21. test configuration test configuration component values test configuration c l (pf) r 1 ( w )r 2 ( w ) 3.3 v standard test 50 990 770 5 v standard test 100 580 390 note: c l includes jig capacitance.
e 2-mbit smartvoltage boot block family 49 see new design recommendations 4.12 ac characteristics read only operations (1) extended temperature prod tbv-80 tbv-80 tbe-120 symbol parameter v cc 3.3 0.3 v (5) 5 v 10% (6) unit load 50 pf 100 pf notes min max min max t avav read cycle time 110 80 ns t avqv address to output delay 110 80 ns t elqv ce# to output delay 2 110 80 ns t phqv rp# to output delay 0.8 0.45 m s t glqv oe# to output delay 2 65 40 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# to output in high z 3 45 25 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# to output in high z 3 45 25 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 ns t elfl t elfh ce# low to byte# high or low 3 00 ns t avfl address to byte# high or low 3 5 5 ns t flqv t fhqv byte# to output delay 3,4 110 80 ns t flqz byte# low to output in high z 3 45 30 ns t plph reset pulse width 7 150 60 ns t plqz rp# low to output high-z 150 60 ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce Ct oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. t flqv , byte# switching low to valid output delay will be equal to t avqv , measured from the time dq 15 /a C1 becomes valid. 5. see test configuration (figure 21), 3.6 v and 3.3 0.3 v standard test component values. 6. see test configuration (figure 21), 5 v standard test component values. 7. the specification t plph is the minimum time that rp# must be held low in order to product a valid reset of the device.
2-mbit smartvoltage boot block family e 50 see new design recommendations 4.13 ac characteristics we#-controlled write operations (1) extended temperature prod tbv-80 tbv-80 tbe-120 sym parameter v cc 3.3 0.3 v (9) 5 v10% (10) unit load 50 pf 100 pf notes min max min max t avav write cycle time 110 80 ns t phwl rp# high recovery to we# going low 0.8 0.45 m s t elwl ce# setup to we# going low 0 0 ns t phhwh boot block lock setup to we# going high 6,8 200 100 ns t vpwh v pp setup to we# going high 5,8 200 100 ns t avwh address setup to we# going high 3 90 60 ns t dvwh data setup to we# going high 4 70 60 ns t wlwh we# pulse width 90 60 ns t whdx data hold time from we# high 4 0 0 ns t whax address hold time from we# high 3 0 0 ns t wheh ce# hold time from we# high 0 0 ns t whwl we# pulse width high 20 20 ns t whqv1 word/byte program time 2,5,8 6 6 s t whqv2 erase duration (boot) 2,5,6,8 0.3 0.3 s t whqv3 erase duration (param) 2,5,8 0.3 0.3 s t whqv4 erase duration (main) 2,5,8 0.6 0.6 s t qvvl v pp hold from valid srd 5,8 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 ns t phbr boot-block lock delay 7,8 200 100 ns
e 2-mbit smartvoltage boot block family 51 see new design recommendations notes: 1. read timing characteristics during program and erase operations are the same as during read-only operations. refer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. refer to command definition table for valid a in . (table 7) 4. refer to command definition table for valid d in . (table 7) 5. program/erase durations are measured to valid srd data (successful operation, sr.7 = 1) 6. for boot block program/erase, rp# should be held at v hh or wp# should be held at v ih until operation completes successfully. 7. time t phbr is required for successful locking of the boot block. 8. sampled, but not 100% tested. 9. see test configuration (figure 21), 3.6 v and 3.3 0.3 v standard test component values. 10. see test configuration (figure 21), 5 v standard test component values.
2-mbit smartvoltage boot block family e 52 see new design recommendations 4.14 ac characteristics ce#-controlled write operations (1, 11) extended temperature prod tbv-80 tbv-80 tbe-120 sym parameter v cc 3.3 0.3 v (9) 5 v10% (10) unit load 50 pf 100 pf notes min max min max t avav write cycle time 110 80 ns t phel rp# high recovery to ce# going low 0.8 0.45 m s t wlel we# setup to ce# going low 0 0 ns t phheh boot block lock setup to ce# going high 6,8 200 100 ns t vpeh v pp setup to ce# going high 5,8 200 100 ns t aveh address setup to ce# going high 90 60 ns t dveh data setup to ce# going high 3 70 60 ns t eleh ce# pulse width 4 90 60 ns t ehdx data hold time from ce# high 0 0 ns t ehax address hold time from ce# high 4 0 0 ns t ehwh we# hold time from ce# high 3 0 0 ns t ehel ce# pulse width high 20 20 ns t ehqv1 word/byte program time 2,5 6 6 s t ehqv2 erase duration (boot) 2,5,6 0.3 0.3 s t ehqv3 erase duration (param) 2,5 0.3 0.3 s t ehqv4 erase duration (main) 2,5 0.6 0.6 s t qvvl v pp hold from valid srd 5,8 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 ns t phbr boot-block lock delay 7,8 200 100 ns notes: see ac characteristics we#-controlled write operations for notes 1 through 10. 11. chip-enable controlled writes: write operations are driven by the valid combination of ce# and we# in systems where ce# defines the write pulse-width (within a longer we# timing waveform), all set-up, hold and inactive we# times should be measured relative to the ce# waveform.
e 2-mbit smartvoltage boot block family 53 see new design recommendations 4.15 erase and program timings extended temperature t a = C40 c to +85 c v pp 5 v 10% 12 v 5% v cc 3.3 0.3 v 5 v 10% 3.3 0.3 v 5 v 10% parameter typ max typ max typ max typ max unit boot/parameter block erase time 0.84 7 0.8 7 0.44 7 0.34 7 s main block erase time 2.4 14 1.9 14 1.3 14 1.1 14 s main block program time (byte) 1.7 1.4 1.6 1.2 s main block program time (word) 1.1 0.9 0.8 0.6 s byte program time 10 10 8 8 s word program time 13 13 8 8 s notes: 1. all numbers are sampled, not 100% tested. 2. max erase times are specified under worst case conditions. the max erase times are tested at the same value independent of v cc and v pp . see note 3 for typical conditions. 3. typical conditions are +25 c with v cc and v pp at the center of the specified voltage range. production programming using v cc = 5.0 v, v pp = 12.0 v typically results in a 60% reduction in programming time. 4. contact your intel representative for information regarding maximum byte/word program specifications.
2-mbit smartvoltage boot block family e 54 see new design recommendations 5.0 ordering information product line designator for all intel flash products density / organization 00x = x8-only (x = 1, 2, 4, 8) x00 = x8/x16 selectable (x = 2, 4, 8) access speed (ns) bv/cv: v cc = 5v architecture b = boot block c = compact 48-lead tso boot block operating temperature t = extended temp blank = commercial temp package e = tsop pa = 44-lead psop tb = ext. temp 44-lead psop e28f2 0 0 cv - t 0 8 t = top boot b = bottom boot t voltage options (v pp /v cc ) v = (5 or 12 / 3.3 or 5) 0530_23 valid combinations: 40-lead tsop 44-lead psop 48-lead tsop 56-lead tsop commercial e28f002bvt60 pa28f200bvt60 e28f200cvt60 e28f200bvt60 e28f002bvb60 pa28f200bvb60 e28f200cvb60 e28f200bvb60 e28f002bvt80 pa28f200bvt80 e28f200cvt80 e28f200bvt80 e28f002bvb80 pa28f200bvb80 e28f200cvb80 e28f200bvb80 e28f002bvt120 pa28f200bvt120 e28f002bvb120 pa28f200bvb120 extended te28f002bvt80 tb28f200bvt80 te28f200cvt80 te28f200bvt80 te28f002bvb80 tb28f200bvb80 te28f200cvb80 te28f200bvb80 summary of line items v cc v pp 40-ld 44-ld 48-ld 56-ld 0 c C C40 c C name 2.7 v 3.3 v 5 v 5 v 12 v tsop psop tsop tsop +70 c +85 c 28f002bv ????? ? ? 28f200bv ???? ? ? ? ? 28f200cv ???? ? ? ?
e 2-mbit smartvoltage boot block family 55 see new design recommendations 6.0 additional information related intel information (1,2) order number document 290530 4-mbit smartvoltage boot block flash memory family datasheet 290539 8-mbit smartvoltage boot block flash memory family datasheet 290599 smart 5 boot block flash memory family 2, 4, 8 mbit datasheet 290580 smart 3 advanced boot block 4-mbit, 8-mbit, 16-mbit flash memory family datasheet 292200 ap-642 designing for upgrade to smart 3 advanced boot block flash memory 292172 ap-617 additional flash data protection using v pp , rp#, and wp# 292148 ap-604 using intels boot block flash memory parameter blocks to replace eeprom 292194 ab-65 migrating smartvoltage boot block flash designs to smart 5 flash 297612 28f200bv/cv 28f002bv specification update notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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